26 set default_commands {
28 Msg Status "\n** The projects in this repository are:"
29 ListProjects $repo_path $list_all
33 # DESCRIPTION: List the projects in the repository. To show hidden projects use the -all option
34 # OPTIONS: all, verbose
41 # DESCRIPTION: Display this help message or specific help for each directive
47 # NAME: CHECKCIENV or CIE
48 # DESCRIPTION: Check that the common environment variables needed for Hog-CI are set
52 \^(CHECKPROJENV|CPE)?$ {#proj
53 set do_checkproj_env 1
54 # NAME: CHECKPROJENV or CPE
55 # DESCRIPTION: Check that the environment variables needed for Hog-CI to run the chosen project are set and point to valid paths
59 \^(CHECKPROJVER|CPV)?$ {#proj
60 set allow_empty_proj 1
61 set do_checkproj_ver 1
62 # NAME: CHECKPROJVER or CPV
63 # DESCRIPTION: Check the project version just before creating the HDL project in Create_Project stage. \
64 The CI job will SKIP the project pipeline, if it the project has not been modified with respect to the target branch.
65 # OPTIONS: ext_path.arg, simcheck, verbose, ci_run
72 # DESCRIPTION: Create the project, replace it if already existing.
73 # OPTIONS: ext_path.arg, lib.arg, vivado_only, vitis_only, verbose
76 \^I(MPL(EMENT(ATION)?)?)?$ {#proj
77 set do_implementation 1
80 # NAME: IMPLEMENTATION or I
81 # DESCRIPTION: Runs only the implementation, the project must already exist and be synthesised.
82 # OPTIONS: check_syntax, ext_path.arg, njobs.arg, no_bitstream, no_reset, recreate, verbose
85 \^SYNT(H(ESIS(E)?)?)? {#proj
89 # DESCRIPTION: Run synthesis only, create the project if not existing.
90 # OPTIONS: check_syntax, ext_path.arg, njobs.arg, recreate, verbose
93 \^S(IM(ULAT(ION|E)?)?)?$ {#proj
96 # NAME*: SIMULATION or S
97 # DESCRIPTION: Simulate the project, creating it if not existing, unless it is a GHDL simulation.
98 # OPTIONS: check_syntax, compile_only, ext_path.arg, lib.arg, recreate, scripts_only, simset.arg, verbose
101 \^W(ORK(FLOW)?)?$ {#proj
102 set do_implementation 1
106 # NAME*: WORKFLOW or W
107 # DESCRIPTION: Runs the full workflow, creates the project if not existing.
108 # OPTIONS: bitstream_only, check_syntax, ext_path.arg, impl_only, njobs.arg, no_bitstream, recreate, synth_only, verbose, vitis_only, xsa.arg
111 \^(CREATEWORKFLOW|CW)?$ {#proj
112 set do_implementation 1
118 # NAME: CREATEWORKFLOW or CW
119 # DESCRIPTION: Creates the project -even if existing- and launches the complete workflow.
120 # OPTIONS: check_syntax, ext_path.arg, njobs.arg, no_bitstream, synth_only, verbose, vivado_only, vitis_only, xsa.arg
123 \^(CHECKSYNTAX|CS)?$ {#proj
124 set do_check_syntax 1
125 # NAME: CHECKSYNTAX or CS
126 # DESCRIPTION: Check the syntax of the project. Only for Vivado, Quartus and Libero projects.
127 # OPTIONS: ext_path.arg, recreate, verbose
130 \^(IPB(US)?)|(X(ML)?)$ {#proj
133 # DESCRIPTION: Copy, check or create the IPbus XMLs for the project.
134 # OPTIONS: dst_dir.arg, generate, verbose
138 set do_list_file_parse 1
140 # DESCRIPTION: Print Hog list file contents in a tree-like fashon.
144 \^(CHECKYAML|YML)?$ {
147 set do_check_yaml_ref 1
148 # NAME: CHECKYML or YML
149 # DESCRIPTION: Check that the ref to Hog repository in the .gitlab-ci.yml file, matches the one in Hog submodule.
158 # DESCRIPTION: Add Hog buttons to the Vivado GUI, to check and recreate Hog list and configuration files.
162 \^(CHECKLIST|CL)?$ {#proj
163 set do_check_list_files 1
164 # NAME: CHECKLIST or CL
165 # DESCRIPTION: Check that list and configuration files on disk match what is on the project.
166 # OPTIONS: ext_path.arg, verbose
171 set argument_is_no_project 1
172 # NAME: COMPSIMLIB or COMPSIM
173 # DESCRIPTION: Compiles the simulation library for the chosen simulator with Vivado.
174 # OPTIONS: dst_dir.arg, verbose
177 \^RTL(ANALYSIS)?$ {#proj
179 # NAME: RTL or RTLANALYSIS
180 # DESCRIPTION: Elaborate the RTL analysis report for the chosen project.
181 # OPTIONS: check_syntax, recreate, verbose
186 # NAME: SIGASI or SIG
187 # DESCRIPTION: Create a .csv file to be used in Sigasi.
194 # DESCRIPTION: Print the design hierarchy for the chosen project.
195 # OPTIONS: compile_order, ext_path.arg, ignore.arg, include_gen_prods, include_ieee, light, output.arg, top.arg, verbose
200 # NAME: VHDL-LS or VHDL
201 # DESCRIPTION: Create a VHDL-LS configuration file for the chosen project.
208 # DESCRIPTION: Create a cocotb Python script to build VHDL/Verilog libraries using runner.build().
209 # OPTIONS: verbose, lib.arg
214 # NAME*: VERSION or VER
215 # DESCRIPTION: Print the version of the chosen Hog project. With -describe, prints the Hog describe string instead.
216 # OPTIONS: describe, verbose
220 if {$directive != ""} {
221 set NO_DIRECTIVE_FOUND 1
231 {no_bitstream "If set, the bitstream file will not be produced."}
232 {recreate "If set, the project will be re-created if it already exists."}
233 {no_reset "If set, runs (synthesis and implementation) won't be reset before launching them."}
234 {check_syntax "If set, the HDL syntax will be checked at the beginning of the workflow."}
235 {njobs.arg 4 "Number of jobs. Default: 4"}
236 {ext_path.arg "" "Sets the absolute path for the external libraries."}
237 {lib.arg "" "Simulation library path, compiled or to be compiled"}
238 {synth_only "If set, only the synthesis will be performed."}
239 {impl_only "If set, only the implementation will be performed. This assumes synthesis was already done."}
240 {scripts_only "If set, the simulation scripts will be generated, but the simulation will not be run."}
241 {compile_only "If set, the simulation libraries will be compiled, but not run."}
242 {bitstream_only "If set, only the bitstream will be produced. This assumes implementation was already done. For a Vivado-Vitis\
243 project this command can be used to generate the boot artifacts including the ELF file(s) without running the\
244 full Vivado workflow."}
245 {vivado_only "If set, and project is vivado-vitis, vitis project will not be created."}
246 {vitis_only "If set, and project is vivado-vitis create only vitis project. If an xsa is not given, a pre-synth xsa will be created."}
247 {xsa.arg "" "If set, and project is vivado-vitis, use this xsa for creating platforms without a defined hw."}
248 {simset.arg "" "Simulation sets to run. HDL sets by name (e.g. sim_1), HLS\
249 (Vitis Unified) sets as csim:<component> or\
250 cosim:<component>. If empty, all enabled simulations are\
252 {all "List all projects, including test projects. Test projects have #test on the second line of hog.conf."}
253 {generate "For IPbus XMLs, it will re create the VHDL address decode files."}
254 {dst_dir.arg "" "For reports, IPbus XMLs, set the destination folder (default is in the ./bin folder)."}
255 {output.arg "" "For tree hierarchy mode, set the output file (default is console)."}
256 {top.arg "" "For tree hierarchy mode, set the top module (default is the top module defined in hog.conf)."}
257 {ignore.arg "" "For tree hierarchy mode, filter's the printed hierarchy to exclude modules that match the given string."}
258 {include_ieee "" "For tree hierarchy mode, include IEEE/STD libraries in the printed hierarchy. (Default 0)"}
259 {include_gen_prods "" "For tree hierarchy mode, include IP generated products in the printed hierarchy. (Default 0)"}
260 {compile_order "" "For tree hierarchy mode, prints compile order instead of hierarchy."}
261 {verbose "If set, launch the script in verbose mode"}
262 {describe "If set, the Hog describe string is returned instead of the version."}
263 {light "For tree hierarchy mode, print a light version of the hierarchy (without file paths)."}
264 {simcheck "If set, checks also the version of the simulation files."}
265 {ci_run "If set, CheckProjVer will run only on the projects that are active in the CI's pipeline.\n\
266 It requires the glab or the gh package installed."}